Integrated circuits which perform arithmetic and logic functions, such as VLSI microprocessors, microcomputers, memories, and application-specific integrated circuits (ASICs), generally output the results of such functions as digital signals. The desired output waveform for such signals is a rapid and noiseless transition from a low voltage representing a "0" logic state to a higher voltage representing a "1" logic state, and vice versa. However, as the speed of the transition is increased by increasing the drive capability of the output buffer circuits, parasitic inductance associated with the interconnection of the output of the integrated circuit to other circuits, and to the power supplies powering the integrated circuit, generates increased noise in the system. This often forces the circuit designer to make a trade-off between the switching speed of the output buffers of the integrated circuit versus the level of noise generated by the switching of the output buffers.
In addition, as the technology for the manufacture of such integrated circuits has advanced, the number of parallel bits of information processed by such circuits has also increased. In the microcomputer field, advancing technology has allowed the advance from four-bit microcontrollers to thirty-two bit microcomputers. Accordingly, since the number of parallel bits output by such devices has increased, the number of output buffers has similarly increased, thereby increasing the noise generated during an output transition.
Furthermore, the increase in the number of parallel output buffers in an integrated circuit further provides for output-to-output sensitivities which are also aggravated by the number of outputs and the increased switching speed. For example, in a microcomputer having sixteen output buffers sharing the same power supply nodes, if fifteen of the outputs are to switch from a "1" state to a "0" state while the sixteenth is to remain at a "0" state, the noise generated by the fifteen switching output buffers will tend to couple, via the shared reference supply node, to the sixteenth output buffer. If the switching speed is sufficient to generate a large amount of noise, the data state presented by the sixteenth output buffer will be disturbed.
Prior techniques have utilized the separation of power supply nodes for output buffers into "quiet" and "noisy" power supply nodes. The push-pull output buffer circuit described in "A LAN System Interface Chip with Selectable Bus Protocols", by Donald Walters, Jr. et al. in 1985 Digest of Technical Papers, 1985 IEEE International Solid-State Circuits Conference (IEEE, 1985), pp. 190-191, shows separate nodes used for the ground reference in the output buffer, with a first ("noisy") ground node used in conjunction with a large pull-down transistor for rapid switching, and a second ("quiet") ground node used in conjunction with a smaller pull-down transistor for DC holding of the low output level. The push-pull output buffer circuit described in copending U.S. application Ser. No. 913,783 filed September 30, 1986 by David Van Lehn and Edward Flaherty, and assigned to Texas Instruments Incorporated, separates both the ground reference nodes and the positive V.sub.dd supply nodes, and accordingly has two pull-up and two pull-down transistors therein. In both of these circuits, means are provided for turning off the drive transistor driving from the "noisy" supply or reference node, once the output has approached its final state. The enabling of the drive transistors from the "quiet" nodes is delayed either by a delay stage, or by making the "quiet" drive transistor significantly smaller than the noisy "drive" transistor. However, during such time as both the "quiet" and "noisy" drive transistors are enabled, noise may couple from the "noisy" node to the "quiet" node.
It is an object of this invention to provide an improved output buffer circuit having separated noisy and quiet reference nodes, where the transistor driving the output from the quiet node is not enabled until the output transition is substantially complete.
It is a further object of this invention to provide such an improved circuit, where feedback from the output node controls the transistor driving from the quiet node.
Other objects and advantages of the instant invention will become apparent to those of ordinary skill in the art having reference to the following specification, in conjunction with the accompanying drawings.